I wired CAS0 AND CAS1 to CASL to activate the DRAM for both banks and CAS1 to A8 for bankswitching in the DRAM -> This should work in theory ;-)
The V9938 only uses the second 64k in graphics mode 6 and 7. To test the full 128k I made a testpicture with 256 colors in graphics mode 7.
The simple DRAM access is in mode 6 and 7 too slow for displaying the screen. Because of that the V9938 changes in these modes to bank interleaving and stores the even bytes in bank 0 and the odd bytes in bank 1.
I tryed a very fast 35ns / 72 MHz DRAM - but it didn't work!
After this I tested the SRAM-replacement with a very fast 128k / 15ns SRAM and a fast 74F374 latch. This works in screen mode 1, but in mode 7 with bank interleaving the timing doesn't fit.
So I decided to use two DRAMS and built a nice tower because I have only one SOJ40-adapter:
With two DRAMS the V9938 works perfect - no screen-artefacts - with the BREADBOARD !
I use only the lower 8 databit of the DRAM - UCAS is pulled up.