Saturday, 25 April 2015

First VDP-testing with 65c02

After some succesful VDP-testing with the ATmega 328p I decided to test it with the real ;-) LC64.
I connected a 32k SRAM with a 74F374 latch clocked by RAS at the DRAM-interface of the VDP, because I had some problems with real DRAM at the breadboard. (The "Steckschwein" developers had the same problems)
Today starts the first tryout with the TMS9129 and the 65c02 on the breadboard. I clocked my Rockwell CPU with the clock-output from the VDP (10.73MHz / 3).

I created three 8x8 characters to show something on my 1084s.
Do you like my Smileys?

This is CSW to the VDP (upper signal) and an adress-line.
The timebase is 40ns/cm.
The CSW has 26ns delay because of the 15ns-GAL-adress-decoder and an OR-gate for combining with R/W.
The 9129 wants the adress-line stable 30ns before / 30ns after CSW goes low.

I think it's OK.

Here is CSW with a data-line (lower signal).
The timebase is 40ns/cm.
The data-line is stable 175ns before / 40ns after CSW goes high.
The 9129 wants the data-line stable 100ns before / 30ns after CSW goes high.

This is perfect.

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